1. Field of the Invention
This invention is directed to a method for forming silicide regions on one or more transistors or other integrated devices formed on a silicon substrate. The silicide regions reduce the contact resistance of electrical connections to the integrated devices, and thus permit the devices to operate at relatively high speeds.
2. Description of the Related Art
Many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques involve the formation of a metal layer over a gate, drain or source region upon which the silicide is desired to be formed. These techniques then use thermal treatment for extended periods of time to react the metal with the silicon composing the gate, source, drain and exposed runners, to form low-resistivity silicide regions. The substrate is further processed by removing the unreacted metal layer. Silicide regions are thus formed over the gate, source and/or drain regions and exposed poly-silicon runners.
Techniques for forming silicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: (1) the metal used to form the silicide and the temperature at which the silicide is formed, must be carefully selected so that the metal diffuses into the silicon to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulating material composing the self-aligning side walls of the gate; (3) the dopants must not segregate appreciably into the silicide regions so that low contact resistance can be achieved; (4) the technique should have a process window that allows the silicide region to be formed on both c-silicon and poly-silicon; (5) the silicide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the silicide regions to prevent an increase in junction leakage. The simultaneous achievement of all of the above-stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself in the occurrence of defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods required by such techniques. If the silicide region extends beyond its design dimensions, it can cause leakage paths between the gate, source/drain and the substrate. There is therefore a great need for a technique that enhances silicidation process margins beyond those conventionally available.
In addition to conventional techniques that use prolonged thermal treatments, some conventional silicidation techniques use ion implantation to achieve formation of the silicide regions. These ion-implantation silicidation techniques use either ion beam mixing of different ion types to produce a silicide of a desired composition, or implantation of a desired species of metal ions in a proportion needed to achieve proper stoichiometry. In either of these two types of techniques, the ion-implantation is so extensive as to be extremely time-consuming, especially if a stoichiometric proportion of ions needed to make the silicide must be implanted into the silicon substrate. In addition, extensive ion implantation will eventually lead to xe2x80x98knock-onxe2x80x99, a phenomenon in which moving ions strike ions previously implanted, driving them further than desired into the silicon substrate. The occurrence of knock-on leads to increased junction leakage. Thus, there is a significant need for a technique that can overcome the above-noted disadvantages of conventional silicidation techniques.
A constraint of all silicidation techniques discussed above is that the silicide thickness of the gate and polysilicon runners is the same as that over the source/drain regions. As source/drain junctions are scaled to shallower depths, the silicide thickness over the source/drain also needs to be lowered accordingly to prevent leakage. However, silicide thickness scaling is not necessary over the gate region and it is in fact advantageous to have thicker silicide over the gate region than over the source/drain regions. Such a silicide layer can be formed either by depositing a thicker metal layer over the gate than that formed over the source/drain regions, or by subjecting the gate to a higher thermal budget. Neither of these two options are feasible using conventional silicide formation techniques.
This invention overcomes the above-noted disadvantages. A preferred embodiment of the invented method includes a step of producing an amorphous region on a silicon body, a step of forming a metal layer in contact with the amorphous region, and a step of irradiating the metal layer with light to diffuse metal into the amorphous region to form an alloy region of silicide composition from the amorphous region. The metal layer is formed on the amorphous region with a thickness that is at least sufficient to produce a stoichiometric silicide over the amorphized region, and the irradiating step proceeds until the metal overlying the alloy region is consumed. The alloy region (particularly in its molten liquid state) has a higher reflectivity than the metal layer, and thus reduces further thermal loading of the alloy region. By reducing the thermal loading of the alloy region upon consumption of the overlying metal, melting beyond the depth of the alloyed region existing upon consumption of the overlying metal can be substantially reduced or arrested.
The step of producing the amorphous region in the silicon body is preferably performed through ion implantation. The depth to which the amorphous region is formed in the silicon body is determined and controlled with high accuracy by selection of the atomic weight of the ion species used for implantation, the implantation energy, and the dosage of ions implanted in the silicon body. Knock-on of metal atoms is not an issue because the amorphization implant is performed prior to metal deposition. The step of forming or positioning the metal layer on the amorphous region is preferably performed by sputtering, evaporating or chemical vapor deposition of the metal onto the silicon body. The metal can be one of a large number of metals, including titanium, cobalt and nickel. The metal thickness is preferably at least sufficient to produce a stoichiometric silicide from the amorphized silicon. The step of irradiating the metal layer is preferably accomplished with pulsed laser light with a fluence sufficient to render the amorphous region molten while the metal layer and the silicon body remain in their solid states. By diffusion of metal from the metal layer caused by the heating produced by the irradiation step, the molten amorphous region becomes an alloy region. To melt the amorphous region while the silicon body and the metal layer remain in their solid states, the fluence of the laser light used to irradiate the metal layer is preferably in a range from 0.1 to 1.0 Joules per square centimeter. The increased reflectivity of the alloy region relative to the metal layer upon consumption of the overlying metal layer reduces thermal loading of the alloy region. Over appropriate fluences for the irradiation step, the energy reflected by the alloy region can be sufficient to arrest further growth of the alloy region. After the irradiation step, the alloy region is in a semi-crystalline state. To further improve its crystallinity and thus reduce its resistivity, the invented method can also include a step of treating the alloy region to convert it into a silicide region with a lower resistivity. Preferably, the treating step is performed by rapid thermal annealing.
In a preferred embodiment, the invented method is used to form self-aligned silicide contacts for the gate, source, drain and connection runners of a metal-insulator-semiconductor field-effect transistor (MISFET). In this embodiment, the metal layer formed in the method has a thickness that is sufficient to produce a substantially stoichiometric silicide on the gate region of the device, and preferably also on the runners that form electrical connections to the integrated device. Irradiation of the metal layer is performed with a fluence that consumes the metal overlying the gate and/or runner regions by diffusion of metal atoms into the molten regions. Alloying occurs only to the melt depth in the gate and runner regions. Upon consumption of the metal layer, the gate and runner alloy regions are exposed. Because the reflectivity of the gate and runner alloy regions formed by diffusion of metal ions is higher than that of the metal layer, further thermal loading of the gate or runner regions is reduced to a degree sufficient to prevent migration of the metal ions beyond the alloy boundaries existing in the gate and runner when the overlying metal layer is consumed. Therefore, further irradiation allows silicide growth to continue in the source and drain regions while substantially reducing or arresting further migration of the metal ions in the gate or runner regions. Accordingly, highly-defined silicides with relatively low resistivities can be formed in the source and drain regions, as well as the gate or runner regions, of the integrated device. Due to thermal trapping caused by the presence of hot source/drains next to the gate, the melt in the gate will proceed deeper than the amorphous depth at the fluence required to completely melt the amorphous region in the source/drains. Hence, over a certain fluence range, amorphization controls the silicide depth in the source/drain regions, and complete consumption of metal controls the silicide depth over the gate. As a result, the silicide thickness over the gate is greater than that over the source/drain. The integrated device formed with the invented method is therefore capable of relatively high operational speeds.
The method of this invention provides several advantages over conventional silicidation techniques. For example, in the methods of this invention, silicidation occurs only in limited portions of the source/drain regions of the silicon body that are rendered amorphous through ion implantation so that the dimensions of the silicide region can be relatively strictly controlled to avoid the formation of leakage paths and other problems that would adversely impact the electronic characteristics of the silicon body and/or any integrated devices formed thereon. Further, the use of light to irradiate the metal layer to diffuse the metal into the amorphous region(s) helps to reduce heating of the silicon body so that integrated devices formed on the silicon body are not subjected to prolonged heating that could damage such devices. In addition, the methods of this invention can be used to perform silicidation at a much faster rate compared to conventional silicidation techniques. The throughput for the silicidation of silicon bodies using the invented method is thus much greater than is possible with conventional silicidation techniques. Full consumption of the metal occurs over the gate and runner regions leading to a thicker silicide over these regions than those over the source/drain regions. Furthermore, upon consumption of the metal layer overlying the gate or runner regions in a preferred embodiment of the invented method, the reflectivity of the gate or runner region increases to reduce thermal loading of the gate or runner region. Irradiation of the metal layer overlying the source and drain regions can thus continue without adversely impacting the gate or runner regions so that relatively low-resistance silicides can be formed in the source and drain regions as well as in the gate and runner regions. With the reduced gate, source, drain and runner silicide resistivities made possible with the invented method, the resulting transistor device is capable of relatively high-speed operation.
These together with other features and advantages, which will become subsequently apparent, reside in the details of construction and operation of the invention as more fully hereinafter described and claimed, reference being made to the accompanying drawings, forming a part hereof wherein like numerals refer to like parts throughout the several views.